Power Conscious BIST Approaches
نویسندگان
چکیده
The System-On-Chip (SOC) revolution has brought some new challenges to both design and test engineers. The most important challenges of today’s VLSI systems testing are linked to test cost, defect coverage and power dissipation. Implementing a self-testable system may reduce test costs as expensive external high performance test equipment is not required and it may increase defect coverage as testing is performed at system speed. Unfortunately, the classic BIST approaches lead to a significant increase of power consumption compared to the system mode and even compared to external testing. The paper will review required changes to be applied to classic BIST techniques for power reduction. A recently developed new BIST approach called functional BIST is introduced and its consequences for power dissipation are discussed.
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